Fast phase locked loop (PLL) lock times may be important, e.g., with integrated voltage regulator (VR) controllers and power management applications to provide for quick state transitions. In addition to fast PLL lock time, reduced clock jitter may also be desired since reduction of jitter is typically proportional to an increase in maximum attainable frequencies and input/output (I/O) transfer rates. Clock latency can be particularly problematic in multi-core systems having multiple clock domain crossings. Accordingly, improved clock generation solutions are desired.